Electrostatic discharge (ESD) is the transfer of electrostatic charge between bodies at different electrostatic potentials (voltages), and can destroy and seriously impair IC devices. ESD protection devices are often built into IC devices, in order to protect the various electronic components with the IC device.
Standards for ESD protection devices are created by a standardization organization, such as the Joint Electron Devices Engineering Council (JEDEC). Some of these standards include the human-body model (HBM), the machine model (MM), and the charge-device model (CDM). Each model characterizes the susceptibility of an electronic device (e.g., an IC) to damage from ESD. The electronic device must be designed to comply with each of these standards.
The HBM simulates the ESD which may occur from the charge that accumulates in a human body discharging through the electronic device. The MM simulates the ESD which may occur from the charge that accumulates in a manufacturing machine (for packaging and probing) discharging through the electronic device. The goal of the CDM is to simulate the discharge from the device through mechanical means which contact is made to a low impedance ground or a charge sink. For example, this may occur when the electronic device slides down a feeder tube during board assembly.
With the decrease in channel lengths in the latest technologies (for example, the 32 nm silicon-on-insulator (SOI) technology or the 28 nm CMOS technology), high current leakage in the current ESD protection devices has been difficult to avoid. In particular, the CDM standard is harder to meet compared to the MM standard or the HBM standard due to the higher current limits. To handle the higher current limits, and comply with the CDM standard, additional clamps are required for the ESD protection device. However, the additional clamps increase the size of the overall ESD protection device. Additionally, each clamp naturally exhibits a current leakage, so the addition of numerous clamps increases the overall current leakage of the ESD protection device.
Aspects of the invention provide an ESD protection device for reducing current leakage, and a related method. In one embodiment, an ESD protection device for an IC is provided. The ESD protection device includes: a resistor-capacitor (RC) timing circuit for selectively turning on the ESD protection device during an ESD event; a trigger circuit for receiving an output of the RC timing circuit and generating a trigger pulse for driving at least one of: a first ESD clamp and a second ESD clamp; and a selection circuit for selecting one of: the trigger circuit or a charge pump for controlling the second ESD clamp. It is only under the condition of an ESD event that the second ESD clamp is turned on. Therefore, the transistors within the second ESD clamp will not exhibit any current leakage, and the overall leakage of the ESD protection device decreases.
Turning to FIG. 1, a schematic diagram of an electrostatic discharge (ESD) protection device 1 according to embodiments of the invention is shown. ESD protection device 1 includes a resistor-capacitor (RC) timing circuit 10 for selectively turning on the ESD protection device 1 during an ESD event. Although FIG. 1 shows a resistor at the top of the RC timing circuit 10 and a capacitor at the bottom of the RC timing circuit 10, it is understood that this is for exemplary purposes only, and that the capacitor may be at the top of the RC timing circuit 10, and the resistor may be at the bottom of the RC timing circuit 10.
An output “A” of the RC timing circuit 10 is sent to a trigger circuit 20. As shown in FIG. 1, the trigger circuit 20 includes a plurality of inverters. Although FIG. 1 only shows 3 inverters, it is understood that the trigger circuit 20 may include any number of inverters, such that the output of the trigger circuit 20 is the opposite of the output of the RC timing circuit 10.
The trigger circuit 20 generates a trigger pulse (not shown) for driving an ESD clamp. As shown in FIG. 1, the output of the trigger circuit 20 is directly connected to a first ESD clamp 30. Although FIG. 1 shows the first ESD clamp 30 as a single n-type field-effect transistor (FET), it is understood that this is for clarity and exemplary purposes only, and that the first ESD clamp 30 may include any number of n-type FETs.
A second ESD clamp 32 is also shown in FIG. 1. Between the first ESD clamp 30 and the second ESD clamp 32 is a selection circuit 50. The selection circuit 50 is configured to select one of: the trigger circuit 20 or a charge pump 40 for controlling the second ESD clamp 32.
The selection circuit 50 includes a pair of transmission gates (not numbered). A first transmission gate of the selection circuit 50 is directly connected to the output of the trigger circuit 20, while the second transmission gate of the selection circuit 50 is directly connected to the charge pump 50. The charge pump 50, as known in the art, generates a negative voltage bias for driving the second transmission gate of the selection circuit 50. Both the first transmission gate and the second transmission gate of the selection circuit 50 are connected to the second ESD clamp 32.
Each transmission gate includes a p-type FET and a n-type FET connected together. As seen in FIG. 1, the p-type FET of the first transmission gate (directly connected to the trigger circuit 20) of the selection circuit 50 receives the “A” output of the RC timing circuit 10, while the n-type FET of the first transmission gate of the selection circuit 50 receives the “B” output of the first inverter of the trigger circuit 20. The p-type FET of the second transmission gate (directly connected to the charge pump 40) of the selection circuit 50 receives the “B” output of the first inverter of the trigger circuit 20, while the n-type FET of the second transmission gate of the selection circuit 50 receives the “A” output of the RC timing circuit 10. That is, the first transmission gate receives the opposite inputs as the second transmission gate, of the selection circuit 50. Therefore, the first transmission gate and the second transmission gate are turned “on” as opposite moments.
Under normal conditions, if the output of the RC timing circuit 10 is a “1”, a “1’ is provided to the p-type FET of the first transmission gate (directly connected to the trigger circuit 20, while a “0” is provided to the n-type FET of the first transmission gate. In other words, the first transmission gate of the selection circuit 50 is turned “off” during normal conditions.
Once an ESD event occurs, a “0” is received from the RC timing circuit 10, which turns on the first transmission gate (directly connected to the trigger circuit 20), while the second transmission gate of the selection circuit 50 (directly connected of the second ESD clamp 32) turns off. Therefore, the charge pump 40 no longer controls the second ESD clamp 32. The output of the trigger circuit 20 is sent to both the first ESD clamp 30 and the second ESD clamp 32. As such, since an ESD event occurred, any additional electrostatic properties are clamped by the first ESD clamp 30 and the second ESD clamp 32. However, since the second ESD clamp 32 is not turned on until the ESD event occurs, the current leakage from the second ESD clamp 32 does not significantly affect the overall current leakage of the ESD protection device 1.
Turning now to FIG. 2, a schematic diagram of an electrostatic discharge protection device 2 according to embodiments of the invention is shown. It is understood that the ESD protection device 2 shown in FIG. 2 is substantially identical to the ESD protection device 1 shown in FIG. 2. However, the “A” input to the transmission gates of the selection circuit 50 is no longer from the output of the RC timing circuit 10. Rather, the “A” input to the transmission gates of the selection circuit 50 is connected to the output of the second inverter in the trigger circuit 20.
Turning now to FIG. 3, a schematic diagram of an integrated circuit (IC) 5 including an electrostatic discharge protection device according to embodiments of the invention is shown. The IC 5 shown in FIG. 3 includes a plurality of I/O devices 7. In between several of these I/O devices 7 may include an ESD protection device 1, as shown in FIGS. 1-2. However, each ESD protection device 1 does not require a separate charge pump 40. Rather, a single charge pump 40 may be provided to each ESD protection device 1.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
This written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims.